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is49fl004t integrated silicon solution, inc. - www.issi.com 1 rev. a 1 9/19 /2013 4 mbi t 3. 3 v olt - onl y firmwar e hub/lp c flas h memory fe a tures ? singl e powe r suppl y operation - lo w voltag e range : 3. 0 v - 3. 6 v ? standar d inte l firmwar e hub/lp c interface - rea d compatibl e t o inte l ? 8280 2 firmwar e hub devices - conform s t o inte l lp c interfac e specification revisio n 1.1 ? memor y configuration - is 49fl004 : 512 k x 8 ( 4 mbit) ? cos t effectiv e sector/bloc k architecture - is 49fl004 : on e hundre d an d twenty - eight unifor m 4 kbyt e sectors , o r eigh t unifor m 64 kbyt e block s (secto r group) ? t o p boo t block - is 49fl004 : 6 4 kbyt e to p boo t block ? automatic erase and program operation - build - i n automati c progra m verificatio n for extende d produc t endurance - t ypica l 2 5 s/byt e programmin g time - t ypica l 5 0 m s sector/block/chi p eras e time ? t wo configurable interfaces - in - syste m hardwar e interface : aut o detectio n of firmwar e hu b (fwh ) o r lo w pi n coun t (lpc) memor y cycl e fo r in - syste m rea d an d write operations - address/address - multiplexe d (a/ a mux) interfac e fo r programmin g o n epro m pro - grammer s durin g manufacturing ? firmwar e hu b (fwh)/lo w pi n coun t (lpc) mode - 3 3 mh z synchronou s operatio n wit h pc i bus - 5 - signa l communicatio n interfac e fo r in - system rea d an d writ e operations - standar d sd p comman d set - data # pollin g an d t oggl e bi t features - register - base d rea d an d writ e protectio n for eac h bloc k (fw h mod e only) - 4 i d pin s fo r multipl e flas h chip s selection (fw h mod e only) - 5 gp i pin s fo r genera l purpos e inpu t register - tbl # pi n fo r hardwar e writ e protectio n t o boot block - wp # pi n fo r hardwar e writ e protectio n t o whole memor y arra y excep t boo t block ? address/addres s multiplexe d (a/ a mux) mode - 1 1 - pi n multiplexe d addres s an d 8 - pi n dat a i/o interface - support s fas t programmin g o n eprom programmers - standar d sd p comman d set - data # pollin g an d t oggl e bi t features ? lower power consumption - t ypica l 2 m a activ e rea d current - t ypica l 7 m a program/eras e current ? hig h produc t endurance - guarante e 100,00 0 program/eras e cycle s per singl e secto r (preliminary) - minimu m 2 0 year s dat a retention ? compatible pin - out and packaging - 32 - pi n ( 8 m m x 1 4 mm ) vsop - 32 - pi n plcc ? hardwar e dat a protection september 2013
is49fl004t integrated silicon solution, inc. - www.issi.com 2 rev. a 1 9/19 /2013 pp general description th e is 49fl 00 4 is 4 mbi t 3. 3 v olt - onl y flas h memorie s use d a s bio s i n pc s an d notebooks . these devices are designed to use a single low voltage, ranging from 3.0 v olt to 3.6 v olt, power supply to perform in - syste m o r o f f - syste m read , eras e an d progra m operations . th e 12. 0 v ol t v powe r suppl y ar e no t require d fo r the progra m an d eras e operation s o f devices . th e device s confor m t o inte l ? lo w pi n coun t (lpc ) interfac e specification revisio n 1. 1 an d als o read - compatibl e wit h inte l 8280 2 firmwar e hu b (fwh ) fo r mos t p c an d noteboo k applications. th e is 49fl 00 4 suppor t tw o configurabl e interfaces : in - syste m hardwar e interfac e whic h ca n automati c de - tec t th e fw h o r lp c memor y cycl e fo r in - syste m rea d an d writ e operations , an d address/addres s multiplexe d (a/ a mux ) interfac e fo r fas t manufacturin g o n epro m programmers . thes e device s ar e designe d t o wor k wit h both inte l famil y chipse t an d non - inte l famil y chipse t platforms , i t wil l provid e p c an d noteboo k manufacturer s great flexibilit y an d simplicit y fo r design , procurement , an d materia l inventory. th e memor y arra y o f is 49fl00 4 i s divide d int o unifor m 4 kbyt e sectors, o r unifor m 6 4 kbyt e block s (secto r grou p - consist s o f sixtee n adjecen t sectors) . th e secto r o r bloc k eras e feature allow s user s t o flexibl y eras e a memor y are a a s smal l a s 4 kbyt e o r a s larg e a s 6 4 kbyt e b y on e singl e erase operatio n withou t affectin g th e dat a i n others . th e chi p eras e featur e allow s th e whol e memor y t o b e erase d i n one singl e eras e operation . th e device s ca n b e programme d o n a byte - by - byt e basi s afte r performin g th e eras e opera - tion. the program operation of is 49fl 004 is executed by issuing the program command code into command register . th e interna l contro l logi c automaticall y handle s th e programmin g voltag e ramp - u p an d timing . th e erase operation of the devices is executed by issuing the sector, block, or chip erase command code into command register . th e interna l contro l logi c automaticall y handle s th e eras e voltag e ramp - u p an d timing . th e preprogramming o n th e arra y whic h ha s no t bee n programme d i s no t require d befor e a n eras e operation . th e device s offe r data# polling and t oggle bit functions in fwh/lpc and a/a mux modes, the progress or completion of program and eras e operation s ca n b e detecte d b y readin g th e data # pollin g o n i/o 7 o r t oggl e bi t o n i/o6. the is 49fl00 4 ha s a 6 4 kbyt e to p boo t block . th e boo t bloc k ca n b e writ e protecte d b y a hardwar e metho d controlled b y th e tbl # pi n o r a register - base d protectio n turne d on/of f b y th e bloc k lockin g register s (fw h mod e only) . the res t o f block s excep t boo t bloc k i n th e device s als o ca n b e writ e protecte d b y wp # pi n o r bloc k lockin g registers (fw h mod e only). th e is 49fl 00 4 ar e manufacture d o n pflash? s advance d nonvolatil e technolog y . th e device s ar e o f fere d in 32 - pi n vso p an d plc c package s wit h optiona l environmenta l friendl y halogen - fre e package.
is49fl004t integrated silicon solution, inc. - www.issi.com 3 rev. a 1 9/19 /2013 f wh f w h 1 l p c la d 1 a / a m u x i / o1 a / a m u x l p c f wh gp i 2 a8 g p i2 f w h 2 i / o2 l a d 2 gp i 3 g p i3 a9 gnd g n d g n d rs t # r st # rs t # f w h3 l a d 3 i / o3 n c nc nc i / o4 r e s r e s v c c v cc v cc r e s r e s i / o5 r / c # c l k c l k r e s i/ o 6 r e s a 10 gp i 4 g p i 4 connection diagrams f wh l p c a / a m u x 4 3 2 1 32 31 30 a / a m u x l p c f wh g p i1 g p i1 a 7 5 29 i c i c ic g pi 0 g p i0 a 6 6 28 g n d g n d g n d w p # t bl # i d 3 i d 2 w p # t bl # r e s r e s a 5 7 a 4 8 a 3 9 a 2 10 27 nc 26 nc 25 v cc 24 o e # nc nc v cc i ni t # nc nc v cc i ni t # i d 1 r e s a 1 11 23 w e # l f r a m e # f w h 4 i d 0 f w h 0 r e s l a d 0 a0 i /o0 12 13 14 15 16 17 22 21 18 19 20 nc i /o7 nc r e s nc r e s 32 - pi n plcc f w h l p c a /a m u x a /a m u x l p c f w h nc nc nc 1 32 o e # i n i t # i n i t # nc nc nc 2 31 w e # lf r a m e # f w h4 nc nc nc 3 30 nc nc nc gnd gnd gnd 4 29 i /o7 r e s r e s i c i c i c 5 28 i /o6 r e s r e s g p i 4 g p i 4 a 1 0 6 27 i /o5 r e s r e s clk clk r/c# 7 26 i /o4 r e s r e s v cc v cc v cc 8 25 i /o3 l a d3 f w h3 nc nc nc 9 24 gnd gnd gnd r st # r st # r st # 10 23 i /o2 l a d2 f w h2 g p i 3 g p i 3 a 9 11 22 i /o1 l a d1 f w h1 g p i 2 g p i 2 a 8 12 21 i /o0 l a d0 f w h0 g p i 1 g p i 1 a 7 13 20 a 0 r e s i d0 g p i 0 g p i 0 a 6 14 19 a 1 r e s i d1 w p # w p # a 5 15 18 a 2 r e s i d2 t b l# t b l# a 4 16 17 a 3 r e s i d3 32 - pi n ( 8m m x 14mm ) vsop
is49fl004t integrated silicon solution, inc. - www.issi.com 4 rev. a 1 9/19 /2013 pin descriptions s y m b o l t y p e i n t e r f a c e d e s c r i p t i o n p p f w h l p c a [ 1 0 : 0 ] i x a dd r e s s i n p u t s : f o r i n p u t i n g t h e m u l t i p l e x a d d r e s s e s a n d c o m m a n d s i n p p m o d e . r o w a n d c o l u m n a d d r e s s e s a r e l a t c h e d d u r i n g a r e a d o r w r i t e c y c l e c o n t r o ll e d b y r / c # p i n . r / c # i x r o w / c o l u m n s e l e c t : t o i n d i c a t e t h e r o w o r c o l u m n a d d r e s s i n p p m od e . w h e n t h i s p i n go e s l o w , t h e r o w a d d r e s s i s l a t c h e d . w h e n t h i s p i n go e s h i g h , t h e c o l u m n ad d r e s s i s l a t c h ed . i / o [ 7 : 0 ] i / o x d a t a i n p u t s / o u t p u t s : u s e d f o r a / a m u x m o d e o n l y , t o i n p u t c o m m a n d / d a t a d u r i n g w r i t e o p e r a t i o n a n d t o o u t p u t d a t a d u r i n g r e a d o p e r a t i o n . t h e da t a p i n s f l o a t t o t r i - s t a t e w h e n o e # i s d i s a b l e d . w e # i x w r i t e e n a b l e : a c t i v a t e t h e d e v i c e f o r w r i t e op e r a t i o n . w e # i s a c t i v e l o w . o e # i x o u t p u t e n a b l e : c o n t r o l t h e d e v i c e ' s o u t p u t b u f f e r s d u r i n g a r e a d c y c l e . o e # i s a c t i v e l o w . ic i x x x i n t e r f a c e c o n f i g u r a t i o n s e l e c t : t h i s p i n d e t e r m i n e s w h i c h m o d e i s s e l e c t e d . w h e n p u ll s h i g h , t h e d e v i c e e n t e r s i n t o a / a m u x m o d e . w h e n p u ll s l o w , f w h / l p c m od e i s s e l e c t e d . t h i s p i n m u s t b e s e t u p d u r i n g p o w e r - u p o r s y s t e m r e s e t , a n d s t a y s n o c h a n g e d u r i n g op e r a t i o n . t h i s p i n i s i n t e r n a ll y p u ll e d d o w n w i t h a r e s i s t o r b e t w e e n 2 0 - 1 0 0 k r s t # i x x x r e s e t : t o r e s e t t h e o p e r a t i o n o f t h e d e v i c e a n d r e t u r n t o s t a n d b y m o d e . i n i t # i x x i n i t i a l i z e : t h i s i s a s e c o n d r e s e t p i n f o r i n - s y s t e m u s e . i n i t # o r r s t # p i n p u ll s l o w w i l l i n i t i a t e a d e v i c e r e s e t . g p i [ 4 : 0 ] i x x f w h / l p c g e n e r a l p u r p o s e i n p u t s : u s e d t o s e t t h e g p i _ r e g f o r s y s t e m d e s i g n p u r p o s e o n l y . t h e v a l u e o f g p i _ r e g c a n b e r e a d t h r o u g h f w h i n t e r f a c e . t h e s e p i n s s h o u l d b e s e t a t d e s i r e d s t a t e b e f o r e t h e s t a r t o f t h e p c i c l o c k c y c l e f o r r e a d o p e r a t i o n a n d s h o u l d r e m a i n n o c h a n g e u n t i l t h e e n d o f t h e r e a d c y c l e . u nu s e d g p i p i n s m u s t n o t b e f l o a t e d . t b l # i x x t o p b l o c k l o c k : w h e n p u ll s l o w , i t e n a b l e s t h e h a r d w a r e w r i t e p r o t e c t i o n f o r t o p bo o t b l o c k . w h e n p u ll s h i g h , i t d i s a b l e s t h e h a r d w a r e w r i t e p r o t e c t i o n . w p # i x x w r i t e p r o t e c t : w h e n p u ll s l o w , i t e n a b l e s t h e h a r d w a r e w r i t e p r o t e c t i o n t o t h e m e m o r y a rr a y e x c e p t t h e t o p b o o t b l o c k . w h e n p u ll s h i g h , i t d i s a b l e s h a r d w a r e w r i t e p r o t e c t i o n . f w h [ 3 : 0 ] i / o x f w h a d d r e s s a n d d a t a : t h e m a j o r i / o p i n s f o r t r a n s m i tt i n g d a t a , a d d r e s s e s a n d c o m m a n d c o d e i n f w h m o d e . f w h 4 i x f w h i n p u t : t o i n d i c a t e t h e s t a r t o f a f w h m e m o r y c y c l e op e r a t i o n . a l s o u s e d t o a b o r t a f h w m e m o r y c y c l e i n p r o g r e s s . l a d [ 3 : 0 ] i / o x l p c a dd r e s s a n d d a t a : t h e m a j o r i / o p i n s f o r t r a n s m i tt i n g d a t a , a d d r e s s e s a n d c o m m a n d c o d e i n l p c m o d e . l f r a m e # i x l p c f r a m e : t o i n d i c a t e t h e s t a r t o f a l p c m e m o r y c y c l e o p e r a t i o n . a l s o u s e d t o a b o r t a l p c m e m o r y c y c l e i n p r o g r e s s . c l k i x x f w h / l p c c l o c k : t o p r o v i d e a s y n c h r o n o u s c l o c k f o r f w h a n d l p c m od e o pe r a t i o n s . i d [ 3 : 0 ] i x i d e n t i f i c a t i o n i n p u t s : t h e s e f o u r p i n s a r e p a r t o f t h e m e c h a n i s m t h a t a ll o w s m u l t i p l e f w h d e v i c e s t o b e a t t a c h e d t o t h e s a m e b u s . t h e s t r a p p i n g o f t h e s e p i n s i s u s e d t o i d e n t i f y t h e c o m p o n e n t . t h e b o o t d e v i c e m u s t h a v e i d [ 3 : 0 ] = 0 0 0 0 b a n d i t i s r e c o m m e n d e d t h a t a l l s u b s e q u e n t d e v i c e s s h o u l d u s e s e q u e n t i a l u p - c o u n t s t r a p p i n g . t h e s e p i n s a r e i n t e r n a ll y p u ll e d - d o w n w i t h a r e s i s t o r b e t w e e n 20 - 10 0 k v c c x x x d e v i c e p o w e r s u p p l y g n d x x x g r o u n d n c x x x n o c o nn e c t i o n r e s x x r e s e r v e d : r e s e r v e d f u n c t i o n p i n s f o r f u t u r e u s e . note : i = input , o = output
is49fl004t integrated silicon solution, inc. - www.issi.com 5 rev. a 1 9/19 /2013 d esc r i p t i on a dd r ess d a t a m a n u f a c t u r e r i d 00000h 00002h 9 d h 7fh d e v i c e i d is 49fl004 4 m b 00001h 6 e h a d d r e s s l a t c h block diagram t b l # wp # init# fwh[3:0 ] o r lad[3:0] fwh 4 o r l f r a m e # cl k gpi[4:0] f w h / l p c m o d e i n t e r f a c e e r a s e / p r o g r a m v o l t a g e g e n e r a t o r h i g h v o l t a g e s w i t c h i/ o b u f f e r s a[10:0] i/o[7:0] we # oe # r/c # ic r s t # p p m o d e i n t e r f a c e c o n t r o l l o g i c d a t a l a t c h s e n s e am p y - d e c o d e r x - d e c o d e r y - g a t i n g m e m o r y a r r a y devic e oper a tion mod e selection th e is 49fl 00 4 ca n operat e i n tw o configurable interfaces: the in - system hardware interface and ad - dress/addres s multiplexe d (a/ a mux ) interfac e con - trolle d b y i c pin . i f th e i c pi n i s se t t o logi c h ig h ( v i h ), th e device s ente r i nt o a/ a mu x interfac e mode . if th e ic pi n i s se t logi c lo w ( v i l ) , th e devic e s wil l b e i n in - system hardwar e interfac e mode . durin g th e in - syste m hard - war e interfac e mode , th e device s ca n automaticall y de - tect the firmware hub (fwh) or low pin count (lpc) memory cycle sent from host system and response to th e comman d accordingly . the i c pi n mus t b e setup durin g power - u p o r syste m reset , an d stay s n o change durin g devic e operation. whe n workin g in - system , typicall y o n a p c o r notebook, th e is 49fl 00 4 ar e connecte d t o th e hos t system throug h a 5 - pi n communicatio n interfac e operate d based o n a 33 - mh z synchronou s clock . th e 5 - pi n interfac e is define d a s fwh[3:0 ] an d fwh 4 pin s unde r fw h mode o r a s lad[3:0 ] an d lframe # pin s unde r lp c mod e for eas y understandin g a s t o thos e existin g compatibl e prod - ucts. when working off - system, typically on a eprom programme r , the devices are operated through 1 1 - pin multiplexe d addres s - a[10:0 ] an d 8 - pi n dat a i/ o - i/o[7: 0 ] interfaces . th e memor y addresse s o f device s ar e in - pu t throug h tw o bu s cycle s a s ro w an d colum n addresses controlled by a r/c# pin. produc t identific a tion th e produc t identificatio n mod e ca n b e use d t o rea d the manufacture r i d an d th e d evic e i d b y a softwar e prod - uc t i d entr y comman d i n bot h in - syste m hardwar e in - terfac e an d a/ a mu x interfac e modes . th e product indentificatio n mod e i s activate d b y three - bus - cycl e com - mand . refe r t o t abl e 1 fo r th e manufacture r i d an d de - vic e i d o f is 49fl00 x an d t abl e 1 4 fo r th e sd p com - man d definition. i n fw h mode , th e produc t identificatio n ca n als o be rea d directl y a t ffbc0000 h fo r manufacture r i d - 9dh an d ffbc0001 h fo r devic e i d i n th e 4 gbyt e system memory map. t able 1: product identification
is49fl004t integrated silicon solution, inc. - www.issi.com 6 rev. a 1 9/19 /2013 il il il ih devic e oper a tio n (continued) th e is 49fl 00 4 provid e thre e level s o f dat a protec - tio n fo r th e critica l bio s cod e o f p c an d notebook . it includes memory hardware write protection, hardware dat a protectio n an d softwar e dat a protection. memo r y hard w ar e writ e protection t he is 49fl00 4 ha s a 6 4 kbyt e to p boo t block . whe n work - in g in - system , th e memor y hardwar e writ e protectio n fea - tur e ca n b e activate d b y tw o contro l pin s - t o p block loc k (tbl# ) an d writ e protectio n (wp# ) fo r bot h fwh an d lp c modes . whe n tbl # i s pulle d lo w ( v ) , th e boot bloc k i s hardwar e writ e protected . a secto r erase , block erase , o r byt e progra m comman d attempt s t o eras e or progra m th e boo t bloc k wil l b e ignored . whe n wp # is pulle d lo w ( v ) , th e bloc k 0 ~ bloc k 6 o f is 49fl00 4 (excep t th e boot block ) ar e hardwar e writ e protected . an y attem p t t o erase o r progra m a secto r o r bloc k withi n thi s are a wil l be ignored. soft w ar e d at a protection th e device s featur e a softwar e dat a protectio n function t o protec t th e devic e fro m a n unintentiona l eras e o r pro - gra m operation . i t i s performe d b y jede c standar d soft - war e dat a protectio n (sdp ) comman d sequences . see t able 14 for sdp command definition. a program op - eration is initiated by three memory write cycles of un - loc k comman d sequence . a chi p (onl y availabl e i n a/a mu x mode) , secto r o r bloc k eras e operatio n i s initiated b y si x memor y writ e cycle s o f unloc k command sequence . durin g sd p comman d sequence , an y invalid comman d o r sequenc e wil l abor t th e operatio n an d force th e devic e bac k t o standb y mode. byt e programming i n progra m operation , th e dat a i s programme d int o the device s (t o a logica l 0 ) o n a byte - by - byt e basis . i n fwh an d lp c modes , a progra m operatio n i s activate d by writin g th e three - byt e comman d sequenc e an d program address/dat a throug h fou r consecutiv e memor y write bot h tbl # an d wp # pin s mus t b e se t lo w (v ) fo r pro - cycles. in a/a mux mode, a program operation is acti - tectio n o r hig h (v ) fo r un - protectio n prio r t o a program vate d b y writin g th e three - byt e comman d sequenc e and o r eras e operation . a logi c leve l chang e o n tbl # o r wp# pi n durin g a progra m o r eras e operatio n ma y caus e un - predictabl e results. the tbl# and wp# pins work in combination with the bloc k lockin g registers . whe n active , thes e pin s write protec t th e appropriat e block s regardles s o f th e associ - ated block locking registers setting. hard w ar e d at a protection hardwar e dat a protectio n protect s th e device s fro m un - intentional erase or program operation. it is performed b y th e device s automaticall y i n th e followin g thre e ways: (a ) v c c detection : i f v c c i s belo w 1. 8 v (typical) , the progra m an d eras e function s ar e inhibited. (b ) writ e inhibi t mode : holdin g an y o f th e signa l oe# low, or we# high inhibits a write cycle (a/a mux mode only). (c ) noise/glitc h protection : pulse s o f les s tha n 5 n s (typi - cal ) o n th e we # inpu t wil l no t initiat e a writ e cycl e (a/a mu x mod e only). progra m address/dat a throug h fou r consecutiv e bus cycles . th e ro w addres s (a1 0 - a0 ) i s latche d o n the fallin g edg e o f r/c # an d th e colum n addres s (a2 1 - a 1 1) i s latche d o n th e risin g edg e o f r/c# . th e dat a i s latched o n th e risin g edg e o f we# . onc e th e progra m operation i s started , th e interna l contro l logi c automaticall y handles th e interna l programmin g voltage s an d timing. a data 0 can not be programmed back to a 1. only eras e operatio n ca n conver t 0 s t o 1s . th e data # poll - in g o n i/o 7 o r t oggl e bi t o n i/o 6 ca n b e use d t o detect whe n th e programmin g operatio n i s complete d i n fwh, lpc, and a/a mux modes. chi p erase the entire memory array can be erased by chip erase operatio n availabl e unde r th e a/ a mu x mod e operated b y epro m programme r only . pre - program s th e device i s no t require d prio r t o th e chi p eras e operation . chip eras e start s immediatel y afte r a six - bus - cycl e chi p erase comman d sequence . al l command s wil l b e ignore d once th e chi p eras e operatio n ha s started . th e data # polling o n i/o 7 o r t oggl e bi t o n i/o 6 ca n b e use d t o detec t the progres s o r completio n o f eras e operation . th e devices wil l retur n bac k t o stand y mod e afte r th e completio n of chi p erase.
is49fl004t integrated silicon solution, inc. - www.issi.com 7 rev. a 1 9/19 /2013 devic e oper a tio n (continued) secto r an d bloc k erase th e is 49fl00 4 con - tain s on e hundre d an d twenty - eigh t unifor m 4 kbyt e sec - tors , o r eigh t unifor m 6 4 kbyt e block s (secto r grou p - consist s o f sixtee n adjecen t sectors) . a secto r erase comman d i s use d t o eras e a n individua l sector . a block eras e comman d i s use d t o eras e a n individua l block. se e t abl e 1 2 - 1 3 fo r sector/bloc k addres s t ables. i n fwh/lp c mode , a n eras e operatio n i s activate d by writin g th e six - byt e comman d sequenc e throug h si x con - secutiv e writ e memor y cycles . i n a/ a mu x mode , an eras e operatio n i s activate d b y writin g th e six - byt e com - man d i n si x consecutiv e bu s cycles . pre - program s the secto r o r bloc k i s no t require d prio r t o a n eras e operation. i/o 7 d at a # polling th e device s provid e a data # pollin g featur e t o indicate th e progres s o r th e completio n o f a progra m o r erase operatio n i n al l modes . durin g a progra m operation , an attemp t t o rea d th e devic e wil l resul t i n th e complement o f th e las t loade d dat a o n i/o7 . onc e th e progra m cycle i s complete , th e tru e dat a o f th e las t loade d dat a i s valid o n al l outputs . durin g a n eras e operation , a n attemp t to rea d th e devic e wil l resul t a 0 o n i/o7 . afte r th e erase cycl e i s complete , a n attemp t t o rea d th e devic e will resul t a 1 o n i/o7. i/o 6 toggl e bit th e is 49fl 00 4 als o provid e a t oggl e bi t featur e to detect the progress or the completion of a program or eras e operation . durin g a progra m o r eras e operation, a n attemp t t o rea d dat a fro m th e device s wil l resul t i n i/ o 6 togglin g betwee n 1 an d 0 . whe n th e progra m or eras e operatio n i s complete , i/o 6 wil l sto p togglin g and valid data will be read. t oggle bit may be accessed at an y tim e durin g a progra m o r eras e operation. reset an y read , program , o r eras e operatio n t o th e devices ca n b e rese t b y th e init # o r rst # pins . init # an d rst# pin s ar e internall y hard - wire d an d hav e sam e functio n to th e devices . th e init # pi n i s onl y availabl e i n fw h and lpc modes. the rst# pin is available in all modes. it is required to drive init# or rst# pins low during sys - tem reset to ensure proper initialization. durin g a memor y rea d operation , pull s lo w th e init # or rst# pin will reset the devices back to standby mode and then the fwh[3:0] of fwh interface or the lad[3: 0 ] o f lp c interfac e wil l g o t o hig h impedanc e state. durin g a progra m o r eras e operation , pull s lo w th e init# o r rst # pi n wil l abor t th e progra m o r eras e operation an d rese t th e device s bac k t o standb y mode . a reset latenc y wil l occu r befor e th e device s resum e t o standby mode when such reset is performed. when a program o r eras e operatio n i s rese t befor e th e completio n o f such operation , th e memor y content s o f device s ma y be - com e i n vali d du e t o a n incomplet e progra m o r erase operation.
is49fl004t integrated silicon solution, inc. - www.issi.com 8 rev. a 1 9/19 /2013 fwh mode oper a tion fw h mod e memo r y read/writ e oper a tion i n fw h mode , th e is 49fl 00 4 ar e connected throug h a 5 - pi n communicatio n interfac e - fwh[3:0 ] and fwh4 pins to work with inte l ? family of i/o controller hub s (ich ) chipse t platform s. th e fw h mod e als o sup - port jedec standard software data protection (sdp) produc t i d entry , byt e program , secto r erase , an d block eras e comman d sequences . th e chi p eras e command sequenc e i s onl y availabl e i n a/ a mu x mode. th e addresse s an d dat a ar e transmitte d throug h th e 4 - bit fwh[3:0] bus synchronized with the input clock on cl k pi n durin g a fw h memor y cycl e operation . the addres s o r dat a o n fwh[3:0 ] bu s i s latche d o n th e ris - ing edge of the clock. the pulse of fwh4 pin inserted fo r on e cloc k indicate s th e star t o f a fw h memor y read o r memor y writ e cycle. onc e th e fw h memor y cycl e i s started , asserte d by fwh4 , a s t a r t valu e 1 1xxb i s expecte d by is 49fl 00 4 a s a vali d comman d cycl e an d i s used t o indicate s th e typ e o f memor y cycl e ( 1 101b fo r fwh memor y rea d cycl e o r 1 1 10b fo r fw h memor y write cycle) . addresse s an d dat a ar e transferre d t o an d from th e devic e decide d b y a serie s o f fields . fiel d sequences an d content s ar e strictl y define d fo r fw h memor y read an d writ e operations . refe r t o t abl e 2 an d 3 fo r fwh memor y rea d c ycl e definitio n an d fw h memor y write cycl e definition. ther e ar e 7 cloc k field s i n a fw h memor y cycl e that give s a 2 8 bi t memor y addres s a2 7 - a 0 throug h fwh [3:0 ] pins , bu t onl y th e las t fiv e addres s field s wil l be decode d b y th e fw h devices . the is 49fl004 decodes a18 - a0 with a19 ignored. the address a22 ha s th e specia l functio n o f directin g read s an d write s to the flash array when a22 = 1 or to the register space wit h a2 2 = 0 . th e a2 7 - a2 3 an d a2 1 - a2 0 ar e dont car e fo r th e device s unde r fw h mode. th e is 49fl 00 4 ar e mappe d withi n th e to p 4 mbyte addres s rang e devote d t o th e fw h device s i n th e 4 gbyte syste m memor y space . pleas e se e t abl e 1 1 fo r system memor y map. fw h abor t oper a tion th e fwh 4 signa l indicate s th e star t o f a memor y cycle o r th e term i nation of a cycle in fwh mode. asserting fwh4 for one or more clock cycle with a valid s t ar t valu e o n fwh[3:0 ] wil l initiat e a memor y rea d o r memory write cycle. if the fwh4 is driven low again for one or mor e cloc k cycle s durin g thi s cycle , thi s cycl e wil l be terminate d an d th e devic e wil l wai t fo r th e abor t com - man d 1 1 1 1b t o re leas e th e fwh[3:0 ] bu s . i f th e abort occur s dur in g th e progra m o r eras e operatio n suc h as checkin g th e operatio n statu s wit h data # pollin g (i/o7) o r t oggl e bi t (i/o6 ) pins , th e rea d statu s cycl e wil l be aborte d bu t th e interna l progra m o r eras e operatio n will no t b e affected . onl y th e rese t operatio n initiate d b y rst# o r init # pi n ca n terminat e th e progra m o r eras e operation.
is49fl004t integrated silicon solution, inc. - www.issi.com 9 rev. a 1 9/19 /2013 fwh mode oper a tion (continued) t able 2: fwh memory read cycle definition c l o c k c yc l e f i e l d f w h [ 3 : 0] d i r ec t i o n d esc r i p t i o n 1 s t a r t 1 101 i n s t a r t o f c y c l e : " 1 1 01b " t o i n d i c a t e t h e s t a r t o f a m e m o r y r ea d c y c l e. 2 i d sel 000 0 t o 1111 in i d s e l e c t c y c l e : i n d i c a t e s w h i ch f w h de v i ce s h o u l d r e s po n d. i f t h e i d se l f i e l d m a t c h e s t h e v a l u e s e t o n i d [ 3 : 0 ] p i n s, t h e n t h e pa r t i c u l a r f w h de v i ce w i l l r e s po n d t o s u b s eq u e n t c o mm a n d s. 3 - 9 i m a dd r yyyy i n a dd r e ss c y c l e s: t h i s i s t h e 2 8 - b i t m e m o r y a dd r e ss. t h e add r e ss e s t r a n s f e r m o s t - s i g n i f i c a n t n i bb l e f i r st a n d l ea s t - s i g n i f i c a n t n i bb l e l a s t . ( i . e . , a 2 7 - 2 4 o n f w h [ 3 : 0 ] f i r s t , a n d a 3 - a 0 o n fw h [ 3 : 0 ] l a s t ) . 10 i m s i z e 0000 i n m e m o r y s i z e c y c l e : i n d i c a t e s h o w m a n y b y t e s w i l l b e or t r a n s f e r r e d d u r i n g m u l t i - b y t e ope r a t i o n s. t h e is 4 9 f l00 x o n l y s u ppo r t " 0 0 00b " f o r o n e b y t e o pe r a t i o n . 11 t a r 0 1111 i n t h e n f l oat t u r n - a r o u n d c y c l e 0 : t h e i n t e l i c h h a s d r i v e n t h e b u s t h en f l oa t i t t o a l l " 1 " s a n d t h e n f l oa t s t h e b u s. 12 t a r 1 1111 ( f l o a t ) f l oa t t h en o u t t u r n - a r o u n d c y c l e 1 : t h e de v i ce t a k e s c o n t r o l o f t h e b u s d u r i n g t h i s c y c l e . 13 r s y n c 0000 ( r ea d y ) o u t r ead y s y n c: t h e f w h de v i ce i n d i c a t e s t h e l e a s t - s i g n i f i c a nt n i bb l e o f d a t a b y t e w i l l b e r ead y i n n e x t c l o c k c y c l e. 14 - 1 5 d a t a yyyy o u t d a t a c y c l e s: t h e 8 - b i t s da t a t r a n s f e rr e d w i t h l ea s t - s i g n i f i c a nt n i bb l e f i r st a n d m o s t - s i g n i f i c a n t n i b b l e l a s t . ( i . e . , i /o 3 - i / o 0 o n l a d [ 3 : 0 ] f i r s t , t h e n i /o 7 - i /o 4 o n f w h [ 3 : 0 ] l a s t ) . 1 6 t a r 0 1111 o u t t h e n f l oat t u r n - a r o un d c y c l e 0 : t h e f w h de v i ce h a s d r i v e n t h e b u s t h e n f l oa t i t t o a l l " 1 " s a n d t h e n f l oa t s t h e b u s. 17 t a r 1 1111 ( f l o a t ) f l oa t t h en in t u r n - a r o u n d c y c l e 1 : t h e i n t e l i c h r e s u m e s c o n t r o l o f t h e b u s d u r i n g t h i s c y c l e . fw h memo r y rea d cycl e w a veforms cl k rs t # o r init # f w h 4 me mo r y read start id sel ad dre ss imsize ta r r s y n c data ta r nex t start fwh[3:0 ] 1101 b id[3:0 ] xxxxb x1xxb a[19:16 ] a[15:12 ] a[11:8 ] a[7:4 ] a[3:0] 0000 b 1111 b tri - stat e 0000 b d[3:0 ] d[7:4] 1111 b tri - state 1101 b 1 clock 1 clock loa d addres s i n 7 clocks 2 clocks 1 clock dat a ou t 2 clocks 2 clo cks 1 clock fro m hos t t o device fro m devic e t o host
is49fl004t integrated silicon solution, inc. - www.issi.com 10 rev. a 1 9/19 /2013 fwh mode oper a tion (continued) t able 3: fwh memory w rite cycle definition c l o c k c yc l e f i e l d f w h [ 3 : 0] d i r ec t i o n d esc r i p t i o n 1 s t a r t 11 1 0 i n s t a r t o f c y c l e : " 11 1 0 b " t o i n d i c a t e t h e s t a r t o f a m e m o r y w r i t e c y c l e . 2 i d sel 000 0 t o 1111 in i d s e l e c t c y c l e : i n d i c a t e s w h i ch f w h de v i ce s h o u l d r e s po n d. i f t h e i d se l f i e l d m a t c h e s t h e v a l u e s e t o n i d [ 3 : 0 ] p i n s, t h e n t h e pa r t i c u l a r f w h de v i ce w i l l r e s po n d t o s u b s eq u e n t c o mm a n d s. 3 - 9 i m a dd r yyyy i n a dd r e ss c y c l e s: t h i s i s t h e 2 8 - b i t m e m o r y a dd r e ss. t h e add r e ss e s t r a n s f e r m o s t - s i g n i f i c a n t n i bb l e f i r st a n d l ea s t - s i g n i f i c a n t n i bb l e l a s t . ( i . e . , a 2 7 - 2 4 o n f w h [ 3 : 0 ] f i r s t , a n d a 3 - a 0 o n fw h [ 3 : 0 ] l a s t ) . 10 i m s i z e 0000 i n m e m o r y s i z e c y c l e : i n d i c a t e s h o w m a n y b y t e s w i l l b e or t r a n s f e r r e d d u r i n g m u l t i - b y t e ope r a t i o n s. t h e is 4 9 f l00 x o n l y s u ppo r t " 0 0 00b " f o r o n e b y t e o pe r a t i o n . 1 1 - 1 2 d a t a yyyy i n d a t a c y c l e s: t h e 8 - b i t s da t a t r a n s f e rr e d w i t h l ea s t - s i g n i f i c a nt n i bb l e f i r st a n d m o s t - s i g n i f i c a n t n i b b l e l a s t . ( i . e . , i /o 3 - i / o 0 o n l a d [ 3 : 0 ] f i r s t , t h e n i /o 7 - i /o 4 o n f w h [ 3 : 0 ] l a s t ) . 1 3 t a r 0 1111 i n t h e n f l oat t u r n - a r o u n d c y c l e 0 : t h e i n t e l i c h h a s d r i v e n t h e b u s t h en f l oa t i t t o a l l " 1 " s a n d t h e n f l oa t s t h e b u s. 14 t a r 1 1111 ( f l o a t ) f l oa t t h en o u t t u r n - a r o u n d c y c l e 1 : t h e de v i ce t a k e s c o n t r o l o f t h e b u s d u r i n g t h i s c y c l e . 15 r s y n c 0000 ( r ea d y ) o u t r ead y s y n c: t h e f w h de v i ce i n d i c a t e s t h a t i t h a s r e c e i v e d t h e da t a o r c o mm a n d . 1 6 t a r 0 1111 o u t t h e n f l oat t u r n - a r o u n d c y c l e 0 : t h e f w h de v i ce h a s d r i v e n t h e b u s t h e n f l oa t i t t o a l l " 1 " s a n d t h e n f l oa t s t h e b u s. 17 t a r 1 1111 ( f l o a t ) f l oa t t h en in t u r n - a r o u n d c y c l e 1 : t h e i n t e l i c h r e s u m e s c o n t r o l o f t h e b u s d u r i n g t h i s c y c l e . fw h memo r y writ e cycl e w a veforms cl k rs t # o r init # f w h 4 me mo r y writ e star t id sel fwh[3:0 ] 1110 b id[3:0 ] xxxxb x1xxb ad dre ss a[19:16 ] a[15:12 ] a[11:8 ] a[7:4 ] a[3:0] imsize 0000 b d[3:0] data d[7:4] t a r r s y n c 1111 b tri - stat e 000 0b ta r 1111 b tri - state nex t start 1110 b 1 clock 1 clock loa d addres s i n 7 clocks 1 cloc k loa d dat a i n 2 clocks 2 clo cks 1 cloc k 2 clo cks 1 clo ck fro m hos t t o device fro m devic e t o host
is49fl004t integrated silicon solution, inc. - www.issi.com 11 rev. a 1 9/19 /2013 fwh mode oper a tion (continued) fw h byt e progra m w a veforms cl k r s t # o r i n i t # f w h 4 memo r y writ e cycl e id sel ad dre ss imsize data t a r r s y n c ta r fwh[3:0 ] 1110 b id[3:0 ] xxxxb x1xx b xxxxb 0101b 0101b 0101 b 0101b 0000b 1010 b 1010b 1111 b tri - stat e 0000b 1111 b tri - state 1 cloc k 1 cloc k loa d "5555h " i n 7 clocks hos t t o device 1 cloc k loa d "aah " i n 2 clocks 2 clocks 1 clock 2 clocks devic e t o host cl k r s t # o r i n i t # f w h 4 2n d start id sel ad dre ss imsize data t a r r s y n c ta r fwh [3:0 ] 1110 b id[3:0 ] xxxxb x1xx b xxxxb 0010 b 1010 b 1010 b 1010 b 000 0b 0101 b 0101 b 1111 b tri - stat e 00 00b 1111 b tri - state 1 cloc k 1 cloc k loa d "2aaah " i n 7 clocks hos t t o device 1 cloc k loa d "55h " i n 2 clocks 2 clo cks 1 clock 2 clo cks devic e t o host cl k r s t # o r i n i t # f w h 4 3r d start id sel ad dre ss imsize data t a r r s y n c ta r fwh [3:0 ] 1110 b id[3:0 ] xxxxb x1xx b xxxxb 0101 b 0101 b 0101 b 010 1b 0000 b 0000 b 1010 b 1111 b tri - stat e 0 000 b 1111 b tri - state 1 cloc k 1 cloc k loa d "5555h " i n 7 clocks hos t t o device 1 cloc k loa d "a0h " i n 2 clocks 2 clo cks 1 clock 2 clo cks devic e t o host cl k r s t # o r i n i t # f w h 4 4t h start id sel ad dre ss imsize data t a r r s y n c ta r fwh [3:0 ] 1110 b id[3:0 ] xxxxb x1xxb a[19:16 ] a[15:12] a[11:8 ] a[7:4] a[3:1] 0000 b d[3:0] d[7:4] 1111 b tri - stat e 00 00 b 1111 b tri - state 1 cloc k 1 cloc k loa d addres s i n 7 clocks hos t t o device 1 cloc k loa d dat a i n 2 clocks 2 clo cks 1 clock 2 clo cks devic e t o host
is49fl004t integrated silicon solution, inc. - www.issi.com 12 rev. a 1 9/19 /2013 fw h sec t o r eras e w a veforms cl k rst # o r i n i t # f w h 4 f w h [ 3 : 0 ] m e m o r y w rit e cycl e i d s e l 1110 b id[3:0 ] xxxxb x1xx b xxxxb add res s 0101 b 0101 b 0101 b 0101 b ims iz e 0000 b dat a 1010 b 1010 b t a r r s y n c 1111 b tri - stat e 0000 b ta r 1111 b tri - stat e 1 cl oc k 1 cloc k loa d "5 555h " i n 7 clock s hos t t o devic e 1 cl oc k loa d "aah " i n 2 clock s 2 cl ock s 1 cl oc k 2 clock s devic e t o hos t cl k rst # o r i n i t # f w h 4 2n d star t i d s e l add res s ims iz e dat a t a r r s y n c ta r f w h [ 3 : 0 ] 1110 b id[3:0 ] xxxxb x1xx b xxxxb 0010 b 1010 b 1010 b 1010 b 0 0 0 0 b 0101 b 0101 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d " 2aaah " i n 7 c l o c k s hos t t o d evic e 1 c l o c k loa d "55h " i n 2 c lock s 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # f w h 4 3r d star t i d s e l add res s ims iz e dat a t a r r s y n c ta r f w h [ 3 : 0 ] 1110 b id[3:0 ] xxxxb x1xx b xxxxb 0101 b 0101 b 0101 b 0 1 0 1 b 0000 b 0000 b 1 0 0 0 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d " 5555h " i n 7 c l o c k s hos t t o d evic e 1 c l o c k loa d "80h " i n 2 c lock s 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # f w h 4 4t h star t i d s e l add res s ims iz e dat a t a r r s y n c ta r f w h [ 3 : 0 ] 1110 b id[3:0 ] xxxxb x1xx b xxxxb 0101 b 0101 b 0101 b 0 1 0 1 b 0000 b 0101 b 1010 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d "5555 " i n 7 c l o c k s hos t t o d evic e 1 c l o c k loa d "aah " i n 2 c lock s 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # f w h 4 5t h star t i d s e l add res s ims iz e dat a t a r r s y n c ta r f w h [ 3 : 0 ] 1110 b id[3:0 ] xxxxb x1xx b xxxxb 0010 b 0010 b 1010 b 1 0 1 0 b 0000 b 0101 b 0 1 0 1 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d " 2aaah " i n 7 c l o c k s hos t t o d evic e 1 c l o c k loa d "55h " i n 2 c lock s 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # f w h 4 6t h star t i d s e l add res s ims iz e dat a t a r r s y n c ta r interna l eras e star t fw h [ 3 : 0 ] 1110 b id[3:0 ] xxxxb x1xx b xxxxb s a [1 9 :1 6 ] s a [1 5 :1 2 ] xxxx b xxxxb 0000 b 0000 b 0011 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k l oa d sect o r add res s i n 7 c l o c k s hos t t o d evic e s a = secto r add res s 1 c l o c k loa d "30h " i n 2 clock s 2 cl ock s 1 cl oc k 2 clock s devic e t o hos t
is49fl004t integrated silicon solution, inc. - www.issi.com 13 rev. a 1 9/19 /2013 fw h bloc k eras e w a veforms cl k rst # o r i n i t # f w h 4 f w h [ 3 : 0 ] m e m o r y w rit e cycl e i d s e l 1110 b id[3:0 ] xxxxb x1xx b xxxxb add res s 0101 b 0101 b 0101 b 0101 b ims iz e 0000 b dat a 1010 b 1010 b t a r r s y n c 1111 b tri - stat e 0000 b ta r 1111 b tri - stat e 1 cl oc k 1 cloc k lo a d "5555 h " i n 7 clock s hos t t o devic e 1 cl oc k loa d "aah " i n 2 clock s 2 cl ock s 1 cl oc k 2 clock s devic e t o hos t cl k rst # o r i n i t # f w h 4 2n d star t i d s e l add res s ims iz e dat a t a r r s y n c ta r f w h [ 3 : 0 ] 1110 b id[3:0 ] xxxxb x1xx b xxxxb 0010 b 1010 b 1010 b 1010 b 0 0 0 0 b 0101 b 0101 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d " 2aaah " i n 7 c l o c k s hos t t o d evic e 1 c l o c k loa d "55h " i n 2 c lock s 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # f w h 4 3r d star t i d s e l add res s ims iz e dat a t a r r s y n c ta r f w h [ 3 : 0 ] 1110 b id[3:0 ] xxxxb x1xx b xxxxb 0101 b 0101 b 0101 b 0 1 0 1 b 0000 b 0000 b 1 0 0 0 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d " 5555h " i n 7 c l o c k s hos t t o d evic e 1 c l o c k loa d "80h " i n 2 c lock s 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # f w h 4 4t h star t i d s e l add res s ims iz e dat a t a r r s y n c ta r f w h [ 3 : 0 ] 1110 b id[3:0 ] xxxxb x1xx b xxxxb 0101 b 0101 b 0101 b 0 1 0 1 b 0000 b 0101 b 1010 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k l oa d "5 555 " i n 7 c l o c k s hos t t o d evic e 1 c l o c k loa d " aah " i n 2 c lock s 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # f w h 4 5t h star t i d s e l add res s ims iz e dat a t a r r s y n c ta r f w h [ 3 : 0 ] 1110 b id[3:0 ] xxxxb x1xx b xxxxb 0010 b 0010 b 1010 b 1 0 1 0 b 0000 b 0101 b 0 1 0 1 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d " 2aaah " i n 7 c l o c k s hos t t o d evic e 1 c l o c k loa d "55h " i n 2 c lock s 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # f w h 4 6t h star t i d s e l add res s ims iz e dat a t a r r s y n c ta r interna l eras e star t fw h [ 3 : 0 ] 1 1 10 b id[3:0 ] xxxxb x1xx b xxxxb b a [1 9 :1 6 ] b a [1 5 :1 4 ] + xxb xxxx b xxxxb 0000 b 0000 b 0101 b 1111 b tri - stat e 0000 b 1111 b tri - stat e 1 cloc k 1 cloc k lo a d bloc k add res s i n 7 clock s hos t t o d evic e b a = bloc k add res s 1 c l o c k loa d "50h " i n 2 c lock s 2 c l o c k s 1 c l o c k 2 clock s devic e t o hos t
is49fl004t integrated silicon solution, inc. - www.issi.com 14 rev. a 1 9/19 /2013 fwh mode oper a tion (continued) fw h gp i registe r rea d w a veforms cl k rst # o r init # f w h 4 memo r y read cycle id sel ad dre ss imsize ta r r s y n c data ta r nex t start fwh[3:0 ] 1101 b id[3:0 ] xxxxb x0xx b 1100b 0000 b 0001 b 0000 b 0000 b 0000 b 1111 b tri - stat e 0000 b d[3:0 ] d[7:4] 1111 b tri - state 1101b 1 cloc k 1 clock loa d addres s "xbc0100h " i n 7 clocks 1 clock 2 clo cks 1 clock dat a ou t 2 clocks 2 clo cks 1 clock fro m hos t t o device fro m devic e t o host fw h bloc k lockin g registe r rea d w a veforms cl k rst # o r init # f w h 4 me mo r y read cycle id sel ad dre ss imsize ta r r s y n c data ta r nex t start fwh[3:0 ] 1101 b id[3:0 ] xxxxb x0xx b a[19:16] 0000 b 0000 b 0000 b 0010 b 0000 b 1111 b tri - stat e 0000 b d[3:0 ] d[7:4] 1111 b tri - state 1101 b 1 cloc k 1 clock loa d addres s "xbx0002h " i n 7 clocks 1 clock 2 clo cks 1 clock dat a ou t 2 clocks 2 clo cks 1 clock fro m hos t t o device fro m devic e t o host
is49fl004t integrated silicon solution, inc. - www.issi.com 15 rev. a 1 9/19 /2013 lpc mode oper a tion lp c mod e memo r y read/writ e oper a tion in lpc mode, the is 49fl 004 use the 5 - pin lpc interfac e include s 4 - bi t lad[3:0 ] an d lframe # pin s to communicat e wit h th e hos t system . th e addresse s and dat a ar e transmitte d throug h th e 4 - bi t lad[3:0 ] bu s syn - chronize d wit h th e inpu t cloc k o n cl k pi n durin g a lpc memor y cycl e operation . th e addres s o r dat a o n lad[3: 0 ] bu s i s latche d o n th e risin g edg e o f th e clock . the puls e o f lframe # signa l inserte d fo r on e o r mor e clocks indicate s th e star t o f a lp c memor y rea d o r writ e cycl e. onc e th e lp c memor y cycl e i s started , asserte d by lframe# , a s t ar t valu e 0000b i s expecte d b y the device s a s a vali d comman d cycle . the n a cyctyp e + di r valu e (010xb fo r memor y rea d cycl e o r 0 1 1xb for memor y writ e cycle ) i s use d t o indicate s th e typ e of memor y cycle . refe r t o t abl e 4 an d 5 fo r lp c m e mory rea d an d writ e cycl e definition. ther e ar e 8 cloc k field s i n a lp c memor y cycl e that give s a 3 2 bi t memor y addres s a3 1 - a 0 throug h lad[3: 0 ] wit h th e most - significan t nibbl e first . th e memory spac e o f is 49fl 00 4 ar e mappe d directl y t o to p of 4 gbyte system memory space. see t able 1 1 for sys - te m memor y map. the is 49fl004 is mapped to the address location of (ffffffff h - fff80000h) , th e a31 - a1 9 mus t be loade d wit h 1 t o selec t an d activat e th e devic e durin g a lp c memor y operation . onl y a1 8 - a 0 i s use d t o de - cod e an d acces s th e 51 2 kbyt e memory.
is49fl004t integrated silicon solution, inc. - www.issi.com 16 rev. a 1 9/19 /2013 lpc mode oper a tion (continued) t able 4: lpc memory read cycle definition c l o c k c y c l e f i e l d l a d [ 3 : 0] d i r e c t i o n d e s c r i p t i o n 1 s t a r t 0 0 00 i n s t a r t of c y c l e : " 0 0 0 0 b" i n d i c a t e s t h e s t a r t of a l p c m e m o r y c y c l e. 2 c y c t y p e + d i r 0 1 0x i n c y c l e t y p e : i n d i ca t e s t h e t y p e o f a l p c m e m o r y r e a d c y c l e . c y c t y pe : bi t s 3 - 2 m u s t be " 0 1 b" f o r m e m o r y c y c l e. d i r : b i t 1 = " 0 b " i n d i c a t es t h e t y p e o f c y c l e f or r e a d. b i t 0 i s r e s e r v e d . 3 - 10 a dd r y y yy i n a d d r e s s c y c l es : t h i s i s t h e 3 2 - b i t m e m o r y a d d r e s s . t h e a d d r es s e s t r a n s f e r m o s t - s i g n i f i ca n t n i b b l e f i r s t a n d l e as t - s i g n i f i c a n t n i b b l e l a s t . ( i . e . , a 31 - 2 8 o n l a d [ 3 : 0] f i rs t , a n d a 3 - a 0 o n l a d [ 3 : 0] l a s t ) . 11 t a r 0 1 1 11 i n t h en f l o a t t u r n - a r o u n d c y c l e 0 : t h e c h i p s e t h a s d r i v e n t h e b u s t o a l l " 1 " s a n d t h e n f l o at t h e b u s . 12 t a r 1 1 1 11 (f l o a t ) f l o a t t h en o u t t u r n - a r o u n d c y c l e 1 : t h e d e v i c e t a k e s co n t r o l o f t h e b u s d u r i n g t h i s c y c l e . 13 s y n c 0 0 00 o u t s y n c : t h e d e v i c e i n d i c a t e s t h e l e a s t - s i g n i f i c a n t n i b b l e of d a t a b y t e w i l l b e r e a d y i n n e x t c l o c k c y c l e. 1 4 - 15 d a t a y y y y o u t d a t a c y c l e s : t h e 8 - b i t s d a t a t r a n s f e r r ed w i t h l e a s t - s i g n i f i c a n t n i b b l e f i r s t a n d m o s t - s i g n i f i c a n t n i b b l e l a s t . ( i . e . , i / o 3 - i / o 0 o n l a d [ 3 : 0 ] f i r s t , t h e n i / o 7 - i / o 4 o n l a d [ 3 : 0 ] l a s t ) . 1 6 t a r 0 1 1 11 o u t t h e n f l o a t t u r n - a r o u n d c y c l e 0: t h e d e v i c e h a s d r i v e n t h e b u s t o a l l " 1 " s a n d t h e n f l o a t s t h e b u s . 17 t a r 1 1 1 11 (f l o a t ) f l o a t t h en in t u r n - a r o u n d c y c l e 1 : t h e c h i p s e t r e s u m es c o n t r ol o f t h e b u s d u r i n g t h i s c y c l e . lp c memo r y rea d cycl e w a veforms cl k rs t # o r init # l f r a m e # start me mo r y read cycle ad dre ss ta r syn c data ta r nex t start lad[3:0 ] 0000 b 010x b 11 11b 1111 b 1 11 1b 11 b + a[17:16] a[15:12 ] a[11:8 ] a[7:4 ] a[3:0 ] 1111 b tri - stat e 0000 b d[3:0 ] d[7:4] 1111 b tri - state 0000 b 1 clock 1 clock loa d addres s i n 8 clocks 2 clocks 1 clock dat a ou t 2 clocks 2 clo cks 1 clock fro m hos t t o device fro m devic e t o host
is49fl004t integrated silicon solution, inc. - www.issi.com 17 rev. a 1 9/19 /2013 lpc mode oper a tion (continued) t able 5: lpc memory w rite cycle definition c l o c k c y c l e f i e l d l a d [ 3 : 0] d i r e c t i o n d e s c r i p t i o n 1 s t a r t 0 0 00 i n s t a r t of c y c l e : " 0 0 0 0 b" t o i n d i c a t e t h e s t a r t of a l p c m e m o r y c y c l e . 2 c y c t y p e + d i r 0 1 1x i n c y c l e t y p e : i n d i ca t e s t h e t y p e o f a l p c m e m o r y w r i t e c y c l e. c y c t y pe : bi t s 3 - 2 m u s t be " 0 1 b" f o r m e m o r y c y c l e. d i r : b i t 1 = " 1 b " i n d i ca t es t h e t y p e o f c y c l e f or w r i t e . b i t 0 i s r e s e r v e d . 3 - 10 a dd r y y yy i n a d d r e s s c y c l es : t h i s i s t h e 3 2 - b i t m e m o r y a d d r e s s . t h e a d d r es s e s t r a n s f e r m o s t - s i g n i f i ca n t n i b b l e f i r s t a n d l e as t - s i g n i f i c a n t n i b b l e l a s t . ( i . e . , a 31 - 2 8 o n l a d [ 3 : 0] f i rs t , a n d a 3 - a 0 o n l a d [ 3 : 0] l a s t ) . 1 1 - 1 2 d a t a y y yy i n d a t a c y c l e s : t h e 8 - b i t s d a t a t r a n s f e r r ed w i t h l e a s t - s i g n i f i c a n t n i b b l e f i r s t a n d m o s t - s i g n i f i c a n t n i b b l e l a s t . ( i . e . , i / o 3 - i / o 0 o n l a d [ 3 : 0 ] f i r s t , t h e n i / o 7 - i / o 4 o n l a d [ 3 : 0 ] l a s t ) . 1 3 t a r 0 1 1 11 i n t h en f l o a t t u r n - a r o u n d c y c l e 0 : t h e c h i p s e t h a s d r i v e n t h e b u s t o a l l " 1 " s a n d t h e n f l o at t h e b u s . 14 t a r 1 1 1 11 (f l o a t ) f l o a t t h en o u t t u r n - a r o u n d c y c l e 1 : t h e d e v i c e t a k e s co n t r o l o f t h e b u s d u r i n g t h i s c y c l e . 15 s y n c 0 0 00 o u t s y n c : t h e d e v i c e i n d i c a t e s t h at i t h as r e c e i v e d t h e da t a or c o mm a n d . 1 6 t a r 0 1 1 11 o u t t h e n f l o a t t u r n - a r o u n d c y c l e 0: t h e d e v i c e h a s d r i v e n t h e b u s t o a l l " 1 " s a n d t h e n f l o a t s t h e b u s . 17 t a r 1 1 1 11 (f l o a t ) f l o a t t h en in t u r n - a r o u n d c y c l e 1 : t h e c h i p s e t r e s u m es c o n t r ol o f t h e b u s d u r i n g t h i s c y c l e . lp c memo r y writ e cycl e w a veforms cl k rs t # o r init # l f r a m e # start me mo r y writ e cycle ad dre ss data ta r syn c ta r nex t start lad[3:0 ] 0000 b 011x b 1111b 1111 b 111 1b a[19:16 ] a[15:12 ] a[11:8 ] a[7:4 ] a[3:0 ] d[3:0] d[7:4] 1111 b tri - stat e 000 0b 1111 b tri - state 0000 b 1 clock 1 clock loa d addres s i n 8 clocks loa d dat a i n 2 clocks 2 clo cks 1 cloc k 2 clo cks 1 clo ck fro m hos t t o device fro m devic e t o host
is49fl004t integrated silicon solution, inc. - www.issi.com 18 rev. a 1 9/19 /2013 lpc mode oper a tion (continued) lp c byt e progra m w a veforms cl k r s t # o r i n i t # l f r a m e # 1s t start memo r y writ e cycle ad dre ss data ta r s yn c ta r lad[3:0 ] 0000 b 011x b 1111b 1111 b 1111b 11xxb 0101b 0101 b 0101b 0101b 1010 b 1010b 1111 b tri - stat e 0000b 1111 b tri - state 1 cloc k 1 cloc k loa d "5555h " i n 8 clock s loa d "aah " i n 2 clocks hos t t o device 2 clocks 1 clock 2 clocks devic e t o host cl k r s t # o r i n i t # l f r a m e # 2n d start me mo r y writ e cycle ad dre ss data ta r syn c ta r lad[3:0 ] 0000 b 011x b 1 111 b 1111 b 111 1b 11xxb 0010 b 1010 b 1010 b 101 0b 0101 b 0101 b 1111 b tri - stat e 00 00b 1111 b tri - state 1 cloc k 1 cloc k loa d "2aaah " i n 8 clock s loa d "55h " i n 2 clocks hos t t o device 2 clo cks 1 clock 2 clo cks devic e t o host cl k r s t # o r i n i t # l f r a m e # 3r d start me mo r y writ e cycle ad dre ss data ta r syn c ta r lad[3:0 ] 0000 b 011x b 1 111 b 1111 b 111 1b 11xxb 0101 b 0101 b 010 1b 0101 b 0000 b 1010 b 1111 b tri - stat e 0 000 b 1111 b tri - state 1 cloc k 1 cloc k loa d "5555h " i n 8 clock s loa d "a0h " i n 2 clocks hos t t o device 2 clo cks 1 clock 2 clo cks devic e t o host cl k r s t # o r i n i t # l f r a m e # 4t h start me mo r y writ e cycle ad dre ss data ta r syn c ta r lad[3:0 ] 0000 b 011x b 1 111 b 1111 b 111 1b a[19:16 ] a[15:12] a[11:8 ] a[7:4] a[3:1] d[3:0] d[7:4] 1111 b tri - stat e 00 00 b 1111 b tri - state 1 cloc k 1 cloc k loa d addres s i n 8 clock s loa d dat a i n 2 clocks hos t t o device 2 clo cks 1 clock 2 clo cks devic e t o host
is49fl004t integrated silicon solution, inc. - www.issi.com 19 rev. a 1 9/19 /2013 lp c sec t o r eras e w a veforms cl k rst # o r i n i t # l f r a m e # 1s t star t m e m o r y w ri t e cycl e add res s dat a t a r syn c ta r l a d [ 3 : 0 ] 0000 b 011x b 1111 b 1111 b 1111 b 11xx b 0101 b 0101 b 0101 b 0101 b 1010 b 1010 b 1111 b tri - stat e 0000 b 1111 b tri - stat e 1 cl oc k 1 cloc k lo a d "5555 h " i n 8 clock s loa d "aah " i n 2 clock s hos t t o devic e 2 cl ock s 1 cl oc k 2 clock s devic e t o hos t cl k rst # o r i n i t # l f r a m e # 2n d star t m e m o r y w ri t e c ycl e add res s dat a t a r syn c ta r l a d [ 3 : 0 ] 0000 b 011x b 1 1 1 1 b 1111 b 1 1 1 1 b 11xx b 0010 b 1010 b 1010 b 1 0 1 0 b 0101 b 0101 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d " 2aaah " i n 8 c l o c k s loa d "55h " i n 2 c lock s hos t t o d evic e 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # l f r a m e # 3r d star t memor y w ri t e c ycl e add res s dat a t a r syn c ta r l a d [ 3 : 0 ] 0000 b 011x b 1 1 1 1 b 1111 b 1 1 1 1 b 11xx b 0101 b 0101 b 0 1 0 1 b 0101 b 0000 b 1 0 0 0 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d " 5555h " i n 8 c l o c k s loa d "80h " i n 2 c lock s hos t t o d evic e 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # l f r a m e # 4t h star t memor y w ri t e c ycl e add res s dat a t a r syn c ta r l a d [ 3 : 0 ] 0000 b 011x b 1 1 1 1 b 1111 b 1 1 1 1 b 11xx b 0101 b 0101 b 0 1 0 1 b 0101 b 0101 b 1010 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k l oa d "5 555 " i n 8 c l o c k s loa d "aah " i n 2 c lock s hos t t o d evic e 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # l f r a m e # 5t h star t memor y w ri t e c ycl e add res s dat a t a r syn c ta r l a d [ 3 : 0 ] 0000 b 011x b 1 1 1 1 b 1111 b 1 1 1 1 b 11xx b 0010 b 1010 b 1 0 1 0 b 1010 b 0101 b 0 1 0 1 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d " 2aaah " i n 8 c l o c k s loa d "55h " i n 2 c lock s hos t t o d evic e 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # l f r a m e # 6t h star t memor y w ri t e c ycl e add res s dat a t a r syn c ta r interna l eras e star t l a d [ 3 : 0 ] 0000 b 011x b 1 1 1 1 b 1111 b 1 1 1 1 b s a [1 9 :1 6 ] s a [1 5 :1 2 ] xxxx b xxxxb xxxxb 0000 b 0011 b 1111 b tri - stat e 0000 b 1111 b tri - stat e 1 cloc k 1 cloc k lo a d secto r add res s i n 8 clock s loa d "30h " i n 2 c lock s 2 cl ock s 1 cl oc k 2 c l o c k s hos t t o d evic e d evic e t o hos t s a = secto r add res s
is49fl004t integrated silicon solution, inc. - www.issi.com 20 rev. a 1 9/19 /2013 lp c bloc k eras e w a veforms cl k rst # o r i n i t # l f r a m e # 1s t star t m e m o r y w ri t e cycl e add res s dat a t a r syn c ta r l a d [ 3 : 0 ] 0000 b 011x b 1111 b 1111 b 1111 b 11xx b 0101 b 0101 b 0101 b 0101 b 1010 b 1010 b 1111 b tri - stat e 0000 b 1111 b tri - stat e 1 cl oc k 1 cloc k lo a d "5555 h " i n 8 clock s loa d "aah " i n 2 clock s hos t t o devic e 2 cl ock s 1 cl oc k 2 clock s devic e t o hos t cl k rst # o r i n i t # l f r a m e # 2n d star t m e m o r y w ri t e c ycl e add res s dat a t a r syn c ta r l a d [ 3 : 0 ] 0000 b 011x b 1 1 1 1 b 1111 b 1 1 1 1 b 11xx b 0010 b 1010 b 1010 b 1 0 1 0 b 0101 b 0101 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d " 2aaah " i n 8 c l o c k s loa d "55h " i n 2 c lock s hos t t o d evic e 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # l f r a m e # 3r d star t memor y w ri t e c ycl e add res s dat a t a r syn c ta r l a d [ 3 : 0 ] 0000 b 011x b 1 1 1 1 b 1111 b 1 1 1 1 b 11xx b 0101 b 0101 b 0 1 0 1 b 0101 b 0000 b 1 0 0 0 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d " 5555h " i n 8 c l o c k s loa d "80h " i n 2 c lock s hos t t o d evic e 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # l f r a m e # 4t h star t memor y w ri t e c ycl e add res s dat a t a r syn c ta r l a d [ 3 : 0 ] 0000 b 011x b 1 1 1 1 b 1111 b 1 1 1 1 b 11xx b 0101 b 0101 b 0 1 0 1 b 0101 b 0101 b 1010 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k l oa d "5 555 " i n 8 c l o c k s loa d "aah " i n 2 c lock s hos t t o d evic e 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # l f r a m e # 5t h star t memor y w ri t e c ycl e add res s dat a t a r syn c ta r l a d [ 3 : 0 ] 0000 b 011x b 1 1 1 1 b 1111 b 1 1 1 1 b 11xx b 0010 b 1010 b 1 0 1 0 b 1010 b 0101 b 0 1 0 1 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 c l o c k 1 c l o c k loa d " 2aaah " i n 8 c l o c k s loa d "55h " i n 2 c lock s hos t t o d evic e 2 c l o c k s 1 c l o c k 2 c l o c k s d evic e t o hos t cl k rst # o r i n i t # l f r a m e # 6t h star t memor y w ri t e c ycl e add res s dat a t a r syn c ta r interna l eras e star t l a d [ 3 : 0 ] 0 0 0 0 b 011x b 1111 b 1111 b 1 1 1 1 b ba[ 1 9 :1 6 ] b a [1 5 :1 4 ] + xxb xxxx b xxxxb xxxxb 0000 b 0101 b 1111 b tri - stat e 0 0 0 0 b 1111 b tri - stat e 1 cloc k 1 cloc k lo a d bloc k add res s i n 8 clock s loa d "50h " i n 2 c lock s hos t t o devic e b a = bloc k add res s 2 cl ock s 1 cl oc k 2 clock s devic e t o hos t
is49fl004t integrated silicon solution, inc. - www.issi.com 21 rev. a 1 9/19 /2013 lpc mode oper a tion (continued) lp c gp i registe r rea d w a veforms cl k rst # o r init # l f r a m e # start memo r y read cycle ad dre ss ta r syn c data ta r nex t start lad[3:0 ] 0000 b 010x b 1 11 1b 1111 b 1 01 1b 1100 b 0000 b 0001 b 0000 b 0000 b 1111 b tri - stat e 0000 b d[3:0 ] d[7:4] 1111 b tri - state 0000 b 1 cloc k 1 clock loa d addres s "ffbc0100h " i n 8 clocks 2 clo cks 1 clock dat a ou t 2 clocks 2 clo cks 1 clock fro m hos t t o device fro m devic e t o host
is49fl004t integrated silicon solution, inc. - www.issi.com 22 rev. a 1 9/19 /2013 registers th e is 49fl 00 4 hav e tw o register s includ e th e gen - era l purpos e input s registe r (gpi_re g - availabl e in fw h an d lp c modes ) an d th e bloc k lockin g register (bl_re g - availabl e i n fw h mod e only) . th e gpi_reg ca n b e rea d a t ffbc0100 h i n th e 4 gbyt e system memor y map . an d th e bl_re g ca n b e rea d through ffbx0002 h wher e x = f - 0h . se e t abl e 8 an d 9 fo r the addres s o f bl_reg. genera l purpos e input s register th e is 49fl 00 4 contai n a n 8 - bi t genera l purpose input s registe r (gpi_reg ) availabl e i n fw h an d lpc modes . onl y bi t 4 t o bi t 0 ar e use d i n curren t version an d bi t 7 t o bi t 5 ar e reserve d fo r futur e use . the gpi_reg is a pass - through register with the value set b y gpi[4:0 ] pi n durin g power - up . th e gpi_re g i s used fo r syste m desig n purpos e only , th e device s d o no t use thi s register . thi s registe r i s rea d onl y an d ca n b e read a t addres s locatio n ffbc0100 h i n th e 4 gbyt e system memor y ma p throug h a memor y rea d cycle . refe r to t abl e 6 fo r genera l purpos e inpu t registe r definition. bloc k lockin g registers th e device s suppor t bloc k read - lock , write - lock , an d lock - dow n feature s throug h a se t o f bloc k lockin g registers. each memory block has an associated 8 - bit read/writ - abl e bloc k lockin g register . onl y bi t 2 t o bi t 0 ar e used i n curren t versio n an d bi t 7 t o bi t 3 ar e reserve d fo r future use . th e defaul t valu e o f bl_re g i s 01h a t powe r up. th e definitio n o f bl_re g i s liste d i n t abl e 7 . th e fw h registe r configuratio n ma p of is 49fl00 4 i s show n i n t abl e 9 . unuse d registe r wil l be rea d a s 00h. t abl e 6 . genera l purpos e input s registe r definition b i t b i t n a m e func t i o n 32 - p l c c p i n # 32 - v s o p p i n# 7 : 5 r e s e r v e d - - 4 g p i 4 g p i _ r e g b i t 4 3 0 6 3 g p i 3 g p i _ r e g b i t 3 3 1 1 2 g p i 2 g p i _ r e g b i t 2 4 1 2 1 g p i 1 g p i _ r e g b i t 1 5 1 3 0 g p i 0 g p i _ r e g b i t 0 6 1 4
is49fl004t integrated silicon solution, inc. - www.issi.com 23 rev. a 1 9/19 /2013 registers (continued) t able 7. block locking register definition b i t func t i on 7 : 3 r e se r ved 2 r e ad - lock " 1 " = p r e v e n t s r ea d ope r a t i o n s i n t h e b l oc k w h e r e se t . " 0 " = n o r m a l ope r a t io n f o r r ead s i n t h e b l oc k w h e r e c l ea r . d e f a u l t s t a t e. 1 lock - d o w n " 1 " = p r e v e n t s f u r t h e r s e t o r c l ea r ope r a t i o n s t o t h e w r i t e - loc k a n d r ead - l o c k b i t s . lock - d o w n o n l y ca n b e se t , b u t n o t c l e a r ed . t h e b l o c k w i l l r e m a i n l o c k ed - do w n u n t i l r e s e t ( w i t h r s t # o r i n i t # ) , o r u n t i l t h e d e v i c e i s po w e r - o n r e s e t . " 0 " = n o r m a l ope r a t io n f o r w r i t e - loc k a n d r ead - loc k b i t a l t e r i n g i n t h e b l oc k w h e r e c l ea r . d e f a u l t s t a t e. 0 wr i t e - lock " 1 " = p r e v e n t s p r og r a m o r e r a s e o p e r a t i o n s i n t h e b l oc k w h e r e se t . d e f a u l t s t a t e. " 0 " = n o r m a l ope r a t io n f o r p r og r a mm i n g a n d e r a s e i n t h e b l oc k w h e r e c l ea r . d a t a b i t [ 7 : 3] b i t 2 b i t 1 b i t 0 r e su l t i n g b l oc k s t a t e 00h 00000 0 0 0 f u l l acces s . 01h 00000 0 0 1 w r i t e l ocked . d e f a u l t s t a t e a t po w e r - u p . 02h 00000 0 1 0 loc k e d ope n ( f u l l ac c es s l o c k e d do w n ) . 03h 00000 0 1 1 w r i t e - l ocke d do w n . 04h 00000 1 0 0 r e a d l o c k ed. 05h 00000 1 0 1 r e a d a n d w r i t e l oc k ed. 06h 00000 1 1 0 r e ad - l oc k e d do w n . 07h 00000 1 1 1 r e ad - l oc k e d a n d w r i t e - l o c k e d do w n .
is49fl004t integrated silicon solution, inc. - www.issi.com 24 rev. a 1 9/19 /2013 registers (continued) t abl e 9 . is 49fl00 4 bloc k lockin g registe r address r e g i s t er b l oc k s i z e ( k b y t es ) p r o t ec t e d b l ock a d d r es s r ange m e m o r y m a p a dd r ess t _ b l o c k _lk 64 70000 h - 7ffffh ff b f0002h t _ m i n u s 01_lk 64 60000 h - 6ffffh ff b e 0002h t _ m i n u s 02_lk 64 50000 h - 5ffffh ff b d 0002h t _ m i n u s 03_lk 64 40000 h - 4ffffh ff b c 0002h t _ m i n u s 04_lk 64 30000 h - 3ffffh ff b b 0002h t _ m i n u s 05_lk 64 20000 h - 2ffffh ff b a 0002h t _ m i n u s 06_lk 64 10000 h - 1ffffh ff b 90002h t _ m i n u s 07_lk 64 00000 h - 0ffffh ff b 80002h
is49fl004t integrated silicon solution, inc. - www.issi.com 25 rev. a 1 9/19 /2013 a/ a mu x mod e oper a tion a/ a mu x mod e read/writ e oper a tion the is 49fl 004 offers a address/address multi - plexed (a/a mux ) mode for off - system operation, typi - call y o n a n epro m programmer , simila r t o a traditional flas h memor y excep t th e addres s inpu t i s multiplexed. in the a/a mux mode, the programmer must drive the oe # pi n t o lo w ( v il ) fo r rea d o r we # pin s t o lo w fo r write operation . th e device s hav e n o chi p enabl e (ce# ) pin fo r chi p selectio n an d activatio n a s traditiona l flash memory . th e r/c# , oe # an d we # pin s ar e use d to activat e th e devic e an d contro l th e powe r . th e 1 1 multi - ple x addres s pin s - a[10:0 ] an d a r/c # pi n ar e use d to loa d th e ro w an d colum n addresse s fo r th e targe t memory location . th e ro w addresse s (interna l addres s a1 0 - a0) ar e latch e d o n th e fallin g edg e o f r/c # pin . t h e column addresse s (interna l addres s a2 1 - a 1 1 ) ar e latche d on th e risin g edg e o f r/c # pi n . th e is 49fl00 4 use s a1 8 - a 0 internall y t o decod e an d acces s th e 25 6 kbytes memor y space . durin g a rea d operation , th e oe # signa l i s use d t o con - tro l th e outpu t o f dat a t o th e 8 i/ o pin s - i/o[7:0] . during a writ e operation , th e we # signa l i s use d t o latc h the inpu t dat a fro m i/o[7:0] . se e t abl e 1 0 fo r bu s operation modes. t able 10. a/a mux mode bus operation modes m ode r s t# o e # w e # a d d r ess i/ o r e a d v ih v il v ih x (1) d o u t wr i t e v ih v ih v il x d in s t a n dby v ih v ih v ih x h i g h z o u t p u t d i s a b l e v ih v ih x x h i g h z r e s e t v il x x x h i g h z p r od u c t i de n t i f i ca t i on v ih v il v ih a 2 - a 2 1 = x, a 1 = v i l , a 0 = v il a n d a 1 = v i h , a 0 = v ih m a n u f a c t u r e r i d (2) a 2 - a 2 1 = x, a 1 = v i l , a 0 = v ih de v i c e i d (2) notes: 1 . x ca n b e v i l or v i h . 2 . refe r t o t abl e 1 fo r th e manufacture r i d an d devic e i d o f devices.
is49fl004t integrated silicon solution, inc. - www.issi.com 26 rev. a 1 9/19 /2013 system memory map table 11. system memory map
is49fl004t integrated silicon solution, inc. - www.issi.com 27 rev. a 1 9/19 /2013 memo r y block s an d addresse s (continued) t abl e 13 . is 49fl00 4 sector/bloc k addres s t able h a r d w a re p r o t ec t i o n b l o c k b l o c k s i z e ( k b y t es ) se c t or se c t o r s i z e ( k b y t es ) a d d r es s r a nge t b l # b l oc k 7 ( b oot b l ock) 64 " " 70000 h - 7f f ffh w p # b l oc k 6 6 4 " " 60000 h - 6f f ffh b l oc k 5 6 4 " " 50000 h - 5f f ffh b l oc k 4 6 4 " " 40000 h - 4f f ffh b l oc k 3 6 4 " " 30000 h - 3f f ffh b l oc k 2 6 4 " " 20000 h - 2f f ffh b l oc k 1 6 4 " " 10000 h - 1f f ffh b l oc k 0 6 4 se c t o r 15 4 0f000 h - 0f f ffh : : : se c t o r 1 4 01000 h - 01 f ffh se c t o r 0 4 00000 h - 00 f ffh
is49fl004t integrated silicon solution, inc. - www.issi.com 28 rev. a 1 9/19 /2013 ms ms command definition t able 14. software data protection command definition c o m m a n d s e quence b u s c y c l e 1 st b u s c y c l e a d d r ( 2) d a t a 2n d b u s c y c l e a d d r d a t a 3 r d b u s c y c l e a d d r d a t a 4 t h b u s c y c l e a d d r d a t a 5 t h b u s c y l ce a d d r d a t a 6 t h b u s c y c l e a d d r d a t a r e ad 1 a d dr d out c h i p e r a s e (1) 6 5 5 5 5h a a h 2 aaa h 5 5h 5 5 5 5h 8 0h 5 5 5 5h a a h 2 aaa h 5 5h 5 5 5 5h 1 0h s e c t or e r a s e 6 5 5 5 5h a a h 2 aaa h 5 5h 5 5 5 5h 8 0h 5 5 5 5h a a h 2 aaa h 5 5h s a ( 3) 3 0h b l o c k e r a s e 6 5 5 5 5h a a h 2 aaa h 5 5h 5 5 5 5h 8 0h 5 5 5 5h a a h 2 aaa h 5 5h b a ( 4) 5 0h b y t e p r o g r a m 4 5 5 5 5h a a h 2 aaa h 5 5h 5 5 5 5h a 0 h a d dr d in p r o d u c t i d e n t r y 3 5 5 5 5h a a h 2 aaa h 5 5h 5 5 5 5h 9 0h p r o d u c t i d e x i t ( 5) 3 5 5 5 5h a a h 2 aaa h 5 5h 5 5 5 5h f 0 h p r o d u c t i d e x i t ( 5) 1 xx x x h f 0h notes: 1 . chi p eras e i s availabl e i n a/ a mu x mod e only. 2 . addres s a[15:0 ] i s use d fo r sd p comman d decodin g internall y an d a1 5 mus t b e 0 i n fwh/lp c an d a/a mu x modes . a - a1 6 = don t car e wher e a i s th e most - significan t addres s o f is 49fl00x. 3 . s a = secto r addres s t o b e erased. 4 . b a = bloc k addres s t o b e erased. 5 . eithe r on e o f th e produc t i d exi t comman d ca n b e used.
is49fl004t integrated silicon solution, inc. - www.issi.com 29 rev. a 1 9/19 /2013 devic e oper a tion s flowcharts au t om a ti c programming star t loa d d at a aa h t o a d d r e s s 5 5 5 5 h loa d dat a 55 h t o a d d r e s s 2 a a a h a d d r e s s i n c r e m e n t loa d d at a a0 h t o a d d r e s s 5 5 5 5 h l o a d p r o g r a m d a t a t o p r o g r a m a d d r e s s i/o 7 = d a t a ? o r i/o 6 s t o p t o g gl e ? n o ye s las t a d d r e s s ? n o ye s p r o g r a m m i n g c o m p l e t e d chart 1. automatic programming flowchart
is49fl004t integrated silicon solution, inc. - www.issi.com 30 rev. a 1 9/19 /2013 devic e oper a tion s flowcharts (continued) au t om a ti c erase star t writ e chip , sector , o r bloc k e r a s e c o m m a n d d a t a = f f h ? o r n o i /o 6 s t o p t o g g le ? ye s e r a s u r e c o m p l e t e d notes: 1. please see t able 12 to t able 13 for sector/bloc k addres s t ables. 2 . onl y eras e on e secto r o r on e bloc k per eras e operation. 3 . whe n th e tbl # pi n i s pulle d lo w ( v i l ), th e boo t bloc k wil l no t b e erased. chi p eras e command secto r eras e command bloc k eras e command loa d d at a aa h t o a d d r e s s 5555 h loa d dat a 55 h t o a d d r e s s 2 a a a h loa d dat a 80 h t o a d d r e s s 5 5 5 5 h loa d d at a aa h t o a d d r e s s 5 5 5 5 h loa d dat a 55 h t o a d d r e s s 2 a a a h loa d dat a 10 h t o a d d r e s s 5555 h (3 ) loa d d at a aa h t o a d d r e s s 5555 h loa d dat a 55 h t o a d d r e s s 2 a a a h loa d dat a 80 h t o a d d r e s s 5 5 5 5 h loa d d at a aa h t o a d d r e s s 5 5 5 5 h loa d dat a 55 h t o a d d r e s s 2 a a a h loa d dat a 30 h t o s a (1, 2, 3 ) loa d d at a aa h t o a d d r e s s 5555 h loa d dat a 55 h t o a d d r e s s 2 a a a h loa d dat a 80 h t o a d d r e s s 5 5 5 5 h loa d d at a aa h t o a d d r e s s 5 5 5 5 h loa d dat a 55 h t o a d d r e s s 2 a a a h loa d dat a 50 h t o (1, 2, 3 ) b a char t 2 . automati c eras e flowchart
is49fl004t integrated silicon solution, inc. - www.issi.com 31 rev. a 1 9/19 /2013 devic e oper a tion s flowcharts (continued) soft w ar e produc t identific a tio n ent r y soft w ar e produc t identific a tio n exit loa d d at a aa h t o a d d r e s s 5555 h loa d d at a aa h t o a d d r e s s 5555 h loa d dat a 55 h t o a d d r e s s 2 a a a h loa d dat a 90 h t o a d d r e s s 5 5 5 5 h loa d dat a 55 h t o a d d r e s s 2 a a a h loa d dat a f0 h t o a d d r e s s 5 5 5 5 h loa d dat a f0 h t o addres s x x x x h o r exi t produc t identificatio n m o d e (3 ) ente r p r o d u c t identificatio n m o d e (1, 2 ) exi t produc t identificatio n m o d e (3 ) notes: 1. after entering product identification mode, the manufacturer id and the device id of is 49fl00x can be read. 2. product identification exit command is required to end the product identification mode and return to standby mode. 3 . eithe r produc t identificatio n exi t comman d ca n b e used , th e devic e return s t o standb y mode. chart 3. software product identification entry/exit flowchart
is49fl004t integrated silicon solution, inc. - www.issi.com 32 rev. a 1 9/19 /2013 absolut e maximu m r a tings (1) t e m pe r a t u r e u n de r bi as - 5 5 o c t o + 125 o c s t o r ag e t e m pe r a t u r e - 6 5 o c t o + 150 o c s u r f ac e m o un t lea d s o l de r i n g t e m pe r a t u r e s t a n da r d pa c k age 240 o c 3 s e c o n d s lead - f r e e p ac k age 260 o c 3 s e c o n d s i n p u t v o l t ag e w i t h r espec t t o g r o u n d o n a l l pi n s ( 2 ) - 0 . 5 v t o v c c + 0 . 5 v a l l o u t p u t v o l t ag e w i t h r espec t t o g r o un d - 0 . 5 v t o v c c + 0 . 5 v v c c (2) - 0 . 5 v t o + 6 . 0 v notes: 1 . stresse s unde r thos e liste d i n absolut e maximu m ratings ma y caus e permanen t damage t o th e device . thi s i s a stres s ratin g only . th e functiona l operatio n o f th e devic e o r an y other condition s unde r thos e indicate d i n th e operationa l section s o f thi s specificatio n i s not implied . exposur e t o absolut e maximu m ratin g conditio n fo r extende d period s ma y affected devic e reliability. 2 . maximu m d c voltag e o n inpu t o r i/ o pin s ar e +6.2 5 v . durin g voltag e transitionin g period, inpu t o r i/ o pin s ma y overshoo t t o v c c + 2. 0 v fo r a perio d o f tim e u p t o 2 0 ns . minimum d c voltag e o n inpu t o r i/ o pin s ar e - 0. 5 v . durin g voltag e transitionin g period , inpu t o r i/o pin s ma y undershoo t gn d t o - 2. 0 v fo r a perio d o f tim e u p t o 2 0 ns. dc and ac oper a ting range p a r t n u m b er is 49fl004 o p e r a t i n g t e m pe r a t u r e 0 o c t o 8 5 o c v c c p o w e r s u pp l y 3 . 0 v - 3 . 6 v
is49fl004t integrated silicon solution, inc. - www.issi.com 33 rev. a 1 9/19 /2013 cc dc characteristics s y m bol p a r a m e t e r c on d i t i o n m i n t y p m a x u n i t s i i i npu t lea k ag e c u rren t f o r i c , i d [ 3 : 0 ] p i n s v i n = 0 v t o v cc , v c c = v c c m ax 1 0 0 a i li i npu t lea k ag e c u rrent v i n = 0 v t o v cc , v c c = v c c m ax a i lo o u t pu t l ea k ag e c u r r e n t v i / o = 0 v t o v c c , v c c = v c c m ax a i sb s t and b y v c c c u r r e n t ( f w h / l p c m od e ) f w h 4 o r l f r a m e # = v i h , f = 3 3 m h z ; v c c = v c c m ax 5 0 0 a i ry r e a d y m od e v c c c u r r e n t ( f w h / l p c m od e ) f w h 4 o r l f r a m e # = v i l, f = 3 3 m h z ; i o u t = 0 m a , v c c = v c c m ax 10 ma i c c 1 v c c a c t i v e rea d c u r r e n t ( f w h / l p c m od e ) f w h 4 o r l f r a m e # = v i l, f = 3 3 m h z ; i o u t = 0 m a , v c c = v c c m ax 2 1 5 ma i c c 2 ( 1 ) v c c p r o g r a m / e ra s e c u rrent 7 2 0 ma v il i npu t lo w v o l t a g e - 0 . 5 0 . 3 v cc v v ih i npu t h i g h v o l t a g e 0 . 7 v cc v c c + 0 . 5 v v ol o u t pu t l o w v o l t a g e i o l = 2 . 0 m a , v c c = v c c m in 0 . 1 v cc v v oh o u t pu t h i g h v o l t age i o h = - 10 0 m a , v c c = v c c m in 0 . 9 v cc v note : 1 . characterize d bu t no t 100 % tested. ac characteristics pi n impedanc e (v = 3. 3 v , f = 1 mhz , t = 25 c ) t y p m ax u n i t s c o nd i t i ons c i / o ( 1) i / o p i n c apa c i t a n ce 12 pf v i / o = 0 v c i n ( 1) i n p u t c apa c i t a n c e 12 pf v i n = 0 v l p i n ( 2) p i n i n d u c t a n ce 20 n h notes: 1 . thes e parameter s ar e characterize d bu t no t 100 % tested. 2 . refe r t o pc i specification.
is49fl004t integrated silicon solution, inc. - www.issi.com 34 rev. a 1 9/19 /2013 ac characteristics (continued) fwh/lp c inter f ac e a c input/outpu t characteristics s y m b ol p ara m e t er c o n d i t i o n m i n m ax u n i t s i o h ( a c ) s w i t c h i n g c u r r e n t h i g h 0 < v o u t < 0 . 3 v cc - 12 v cc ma 0 . 3 v cc < v o u t < 0 . 9 v cc - 17 . 1 ( v cc - v o u t ) m a 0 . 7 v cc < v o u t < v cc e q u a t i on c ( 1 ) ( t e s t p o i n t ) v o u t = 0 . 7 v cc - 32 v cc ma i o l ( a c ) s w i t c h i n g c u r r e n t l ow v cc > v o u t > 0 . 6 v cc 16 v cc ma 0 . 6 v cc > v o u t > 0 . 1 v cc - 17 . 1 ( v cc - v o u t ) m a 0 . 18 v cc > v o u t > 0 e q u a t i on d ( 1 ) ( t e s t p o i n t ) v o u t = 0 . 18 v cc 38 v cc ma i cl l o w c l a m p c u r r e n t - 3 < v i n < - 1 - 25 + ( v i n + 1) / 0 . 0 1 5 m a i ch h i g h c l a m p c u r r e n t v cc + 4 > v i n > v cc + 1 25 + ( v i n - v cc - 1) / 0 . 0 1 5 ma s l e w r ( 2 ) o u t p u t r i s e s l e w r a t e 0 . 2 v cc - 0 . 6 v cc l o ad 1 4 v / n s s l e w f ( 2 ) o u t p u t f a l l s l ew r a te 0 . 6 v cc - 0 . 2 v cc l o ad 1 4 v / n s notes: 1 . se e pc i specification. 2 . pc i specificatio n outpu t loa d i s used. fwh/lp c inter f ac e cloc k characteristics sy m b ol pa r a m e t e r m i n m a x u n i t s t c y c c l oc k c y c l e t i m e 30 n s t h i g h c l o c k h i g h t i m e 11 ns t l o w c l oc k lo w t i m e 1 1 n s c l o c k s l e w r a t e 1 4 v / n s i n i t # o r r s t # s l e w r a t e 50 m v / n s
is49fl004t integrated silicon solution, inc. - www.issi.com 35 rev. a 1 9/19 /2013 ac characteristics (continued) fwh/lp c inter f ac e cloc k w a veform 0. 5 v c c 0. 4 v c c 0. 3 v c c t h i g h t cy c t lo w 0. 6 v c c ( m in im u m ) 0. 2 v c c fwh/lp c inter f ac e measuremen t conditio n p arameters sy m b o l v a l u e u n i t s v t h 1 0 . 6 v cc v v t l 1 0 . 2 v cc v v t e s t 0 . 4 v cc v v m a x 1 0 . 4 v cc v i n p u t s i g n a l e dg e r a t e 1 v / n s note : 1 . th e inpu t tes t environmen t i s don e wit h 0. 1 v c c o f overdriv e ove r v i h an d v i l . timin g parameter s must b e me t wit h n o mor e overdriv e tha t this . v ma x specifie s th e maximu m peak - to - pea k wavefor m allowed fo r measurin g inpu t timing . productio n testin g ma y us e differen t voltag e values , bu t mus t correlate result s bac k t o thes e parameter. fwh/lp c memo r y read/writ e oper a tion s characteristics sy m b ol pa r a m e t e r m i n m a x un i t s t c y c c l oc k c y c l e t i m e 30 n s t su i n p u t s e t u p t i m e 7 n s t h i n p u t h o l d t i m e 0 n s t v a l c l o c k t o d a t a o u t 2 1 1 n s t on c l o c k t o a c t i v e t i m e (f l o a t t o a c t i v e de l a y ) 2 n s t o f f c l oc k t o i n ac t i v e t i m e ( ac t i v e t o f l o a t d e l a y ) 28 n s
is49fl004t integrated silicon solution, inc. - www.issi.com 36 rev. a 1 9/19 /2013 ac characteristics (continued) fwh/lp c inpu t timin g p arameters cl k f w h [ 3 : 0 ] o r l a d [3 :0 ] (vali d inpu t data ) t s u i n p u t v a l i d v t e s t t h v t h v t l v ma x fwh/lp c outpu t timin g p arameters cl k f w h [ 3 : 0 ] o r l a d [ 3 : 0 ] ( v a l i d o u t p u t d a t a ) f w h [ 3 : 0 ] o r l a d [ 3 : 0 ] ( f l o a t o u t p u t d a t a ) v t e s t t va l t of f t o n v t h v t l
is49fl004t integrated silicon solution, inc. - www.issi.com 37 rev. a 1 9/19 /2013 ac characteristics (continued) fwh/lp c rese t oper a tio n characteristics s y mbol p a r ameter m in m ax units t prst re s et a c tive t i m e to v c c stable 1 m s t krst re s et a c tive t i m e to clock stable 100 s t rs t p re s et pul s e w i dth 100 ns t rs t f re s et a c tive to o utput fl o at delay 50 ns t ( 1 ) rst re s et ina c tive t i m e to in p ut a c tive 1 s note : 1 . ther e wil l b e a 1 0 s rese t latenc y i f a rese t procedur e i s performe d durin g a programmin g o r erase operation. fwh/lp c rese t a c w a veforms v c c t p r s t cl k r s t # / i n i t # f w h [ 3 : 0 ] o r l a d [ 3 : 0 ] f w h 4 o r l f r a m e # t k r s t t r s t f t r s t p t rs t a/ a mu x mod e inpu t tes t measuremen t conditio n p arameters 3. 0 v inpu t 0. 0 v 1. 5 v a c m e a s u r e m e n t leve l a/ a mu x mod e tes t loa d condition t o t e s t e r t o du t c l 3 0 p f
is49fl004t integrated silicon solution, inc. - www.issi.com 38 rev. a 1 9/19 /2013 ac characteristics (continued) a/ a mu x mod e rea d oper a tion s characteristics s y m bol p a r a m e t e r m i n m a x u n i t s t rc r ea d c y c l e t i m e 2 7 0 n s t a c c a dd re s s t o ou t p u t d e l a y 1 2 0 n s t r s t r s t # h i g h t o r o w a d d r e s s s e t - u p t i m e 1 m s t as r / c # a dd r e s s s e t - u p t i m e 45 ns t ah r / c # a dd r e s s h o l d t i m e 45 ns t oe o e # t o o u t pu t d e l a y 50 ns t df o e # t o o u t pu t h i g h z 0 3 0 n s t oh ou t pu t h o ld f r o m o e # o r a d dr e ss , w h i c he v e r o cc u re d f i r s t 0 n s t v c s v c c s e t - u p t i m e 50 s a/ a mu x mod e rea d oper a tion s a c w a veforms r s t # a d d r e s s t rs t ro w a d d r e s s t r c c o l u m n addres s r / c # oe # we # t a s t a h t a s t a h t ac c t o e t d f t o h o u t p u t v c c t vc s hig h z o u t p u t v a l i d
is49fl004t integrated silicon solution, inc. - www.issi.com 39 rev. a 1 9/19 /2013 ac characteristics (continued) a/ a mu x mod e writ e (program/erase ) oper a tion s characteristics s y m b o l p a r a m e t e r m i n m a x u n i t s t r s t r s t # h i g h t o r o w a d d r e s s s e t - u p t i m e 1 m s t as r / c # a dd r e s s s e t - u p t i m e 50 ns t ah r / c # a dd r e s s h o ld t i m e 50 ns t c w h r / c # t o w e # h i g h t i m e 5 0 n s t oes o e # h i g h s e t - u p t i m e 20 ns t oeh o e # h i g h h o ld t i m e 20 ns t ds d a t a s e t - u p t i m e 50 ns t dh d a t a h o l d t i m e 5 n s t wp w r i t e p u l s e w i d t h 100 ns t w p h w r i t e p u l s e w i d t h h i gh 100 ns t bp b yt e p rogra m m i n g t i m e 40 s t ec c h i p , s e c t o r o r b l o c k e ra s e c yc l e t i m e 8 0 m s t v c s v c c s e t - u p t i m e 50 s a/ a mu x mod e writ e oper a tion s a c w a veforms r s t # t rs t t r c a d d r e s s ro w a d d r e s s c o l u m n addres s r / c # oe # we # t vc s t a s t a h t a s t a h t cw h t oe h t oe s t d s t d h o u t p u t hig h z i n p u t d a t a v c c
is49fl004t integrated silicon solution, inc. - www.issi.com 40 rev. a 1 9/19 /2013 d a t a t ac characteristics (continued) a/ a mu x mod e byt e progra m oper a tion s a c w a veforms a d d r e s s 4 - b y t e p r o g r a m c o m m a n d 555 5 2 a a a 555 5 b y t e addres s r / c # we # t cw h t w p t wp h b p oe # t d s t d h d a t a a a 5 5 a 0 i n p u t v a l i d d a t a a/ a mu x mod e chi p eras e oper a tion s a c w a veforms 6 - b y t e c h i p e r a s e c o m m a n d a d d r e s s 555 5 2 a a a 555 5 555 5 2 a a a 555 5 r / c # we # t cw h t w p t wp h t e c oe # t d s t d h d a t a i n a a 5 5 8 0 a a 5 5 1 0
is49fl004t integrated silicon solution, inc. - www.issi.com 41 rev. a 1 9/19 /2013 ac characteristics (continued) a/ a mu x mod e sec t or/bloc k eras e oper a tion s a c w a veforms 6 - b y t e b l o c k e r a s e c o m m a n d a d d r e s s r / c # 555 5 2 a a a 555 5 555 5 2 a a a s e c t o r o r bloc k a d d r e s s we # t cw h t w p t wp h t e c oe # t d s t d h d a t a i n a a 5 5 8 0 a a 5 5 3 0 / 5 0 a/ a mu x mod e t oggl e bi t a c w a veforms a d d r e s s r o w c o l u m n r / c # we # oe # i/o 6 t oe h d t o e d note : 1 . t ogglin g oe # wil l operat e t oggl e bit. 2 . i/o 6 ma y star t an d en d fro m 1 o r 0 i n random.
is49fl004t integrated silicon solution, inc. - www.issi.com 42 rev. a 1 9/19 /2013 ac characteristics (continued) a/ a mu x mod e d a t a # pollin g a c w a veforms a d d r e s s r o w c o l u m n r / c # we # oe # i/o 7 t oe h d t o e d # d # d # d note : t ogglin g oe # wil l operat e data # polling. program/erase performance p a r a m e t e r u n i t t yp m ax r e m a r ks s e c t o r / b l o c k e r as e t i m e m s 50 80 f r o m w r i t i n g e r as e co mm a n d t o e r a s e c o m p l e t i o n c h i p e r as e t i m e m s 50 80 f r o m w r i t i n g e r as e co mm a n d t o e r a s e c o m p l e t i o n b y t e p r o g r a m m i n g t i m e s 25 40 e x c l u d e s t h e t i m e of f o u r - c y c l e p r og r am co m m a n d e x e c u t i o n note : thes e parameter s ar e characterize d bu t no t 100 % tested. reliability characteristics (1) pa r a m e t e r m i n t y p u n i t t es t m e t hod e n d u r a n c e 100 , 00 0 ( 2 ) c y c l es j e d e c s t a n da r d a 1 17 d a t a r e t e n t i o n 2 0 y ea r s j e d e c s t a n da r d a 103 e s d - h u m a n b od y m odel 2 , 000 > 4 , 000 v o l t s j e d e c s t a n da r d a 1 14 e s d - m a c h i n e m o del 200 > 400 v o l t s j e d e c s t a n da r d a 1 15 la t c h - u p 10 0 + i c c 1 m a j e d e c s t a n da r d 78 notes : 1 . thes e parameter s ar e characterize d bu t no t 100 % tested. 2 . preliminar y specificatio n onl y an d wil l b e formalize d afte r cyclin g qualificatio n test.
is49fl004t integrated silicon solution, inc. - www.issi.com 43 rev. a 1 9/19 /2013 p ackag e typ e inform a tion 32v 32 - pi n thi n smal l outlin e packag e (vso p - 8 m m x 1 4 mm) ( measur e i n millimeters) pi n 1 i.d . 1 . 0 5 0 . 9 5 0 . 2 7 0 . 1 7 8.1 0 7 . 9 0 0 . 5 0 bs c 1 2 . 5 0 1 2 . 3 0 1 4 . 2 0 1 3 . 8 0 0 . 1 5 0 . 0 5 1 . 2 0 ma x 0 . 2 5 0 . 2 0 0 0 .1 0 5 0 . 7 0 0 . 5 0 32j 32 - pin plastic leaded chip carrier (measured in millimeters) 1 2 . 5 7 1 2 . 3 2 1 1 . 5 1 1 1 . 3 5 1 5 . 1 1 1 4 . 8 6 1 4 . 0 5 pi n 1 i. d . 3 . 5 6 3 . 1 8 2 . 4 1 1 . 9 3 0 . 7 4 x 3 0 1 3 . 8 9 s e a t i n g p l a n e 0 . 8 1 0 . 6 6 1 . 2 7 t y p . 0 . 5 3 0 . 3 3 1 3 . 4 6 1 2 . 4 5 to p vie w sid e view
is49fl004t integrated silicon solution, inc. - www.issi.com 44 rev. a 1 9/19 /2013 product ordering inform a tion is49fl00x t - 3 3 j c e environmenta l attribute e = lead - fre e package t emperatur e range c = 0 c t o +85c packag e t ype j = 32 - pi n plasti c j - leade d chi p carrie r (32j) v = 32 - pi n ( 8 m m x 1 4 mm ) vso p (32v) speed option boo t bloc k location t = t o p boo t block device number is49fl00 4 ( 4 mbit)
is49fl004t integrated silicon solution, inc. - www.issi.com 45 rev. a 1 9/19 /2013 ordering information: density frequency (mhz) order part number package 4m 33 is49fl004t - 33jce 32 - pi n plcc is49fl004t - 33vce 32 - pi n ( 8 m m x 1 4 mm ) vso p

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